The present invention relates to a device for controlling the gate drive voltage in a liquid crystal display.
A liquid crystal display comprises a liquid crystal panel and a backlight module. The backlight module provides planar light to the liquid crystal panel. The liquid crystal panel comprises an array substrate, a color filter substrate and a liquid crystal layer, and the liquid crystal layer is formed through injecting liquid crystal into the space between the array substrate and the color filter substrate that face each other.
The array substrate comprises a plurality of pixel units, and each of the pixel units may be formed with a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors (TFTs), a plurality of pixel electrodes, a plurality of common electrode lines and the like. The gate lines, the data lines, and the common electrode lines can be collectively referred to as the signal lines. For example, the gate lines and the common electrodes line are laterally provided on the array substrate, the data lines are longitudinally provided on the array substrate, and the TFTs are provided at the intersections of the gate lines and the data lines. The TFTs are active switching elements and each may be formed with a gate electrode, a gate insulating layer, an active layer, a TFT channel, a source electrode, a drain electrode, a passivation layer and the like. The gate electrode is connected or integrally formed with one of the gate lines, the source electrode is connected or integrally formed with one of the data lines, and the drain electrode is normally connected with one of the pixel electrodes through a passivation layer via hole. When a turn-on (“ON”) voltage is input into one of the gate lines, the active layer of the TFT that is connected with the gate line becomes conductive, and the data signal over the data line connected with the TFT travels, through the TFT channel region, from the source electrode to the drain electrode, and ultimately into the pixel electrode. After receiving the signal input, the pixel electrode, together with a common electrode provided on the color filter substrate, forms an electric field to drive the liquid crystal to rotate.
The drive devices for driving the liquid crystal display include a BLU controller, a timing controller, a gate drive circuit, a data driver and the like.
Liquid crystal displays tend to have a thinner appearance and a lower manufacturing cost in recent years. With the development of liquid crystal displays, there emerges a liquid crystal display without an individual gate drive print circuit board (referred to as GATE PCB-less LCD). In a GATE PCB-less LCD, signals originally transmitted by the gate drive integrated circuit board are transmitted by circuits that are directly formed on the glass substrate used to form the array substrate, that is, the gate drive circuits are formed on the array substrate, and thus it is not necessary to form the individual gate drive integrated circuit board. The liquid crystal display, therefore, has a reduced thickness and a lowered manufacturing cost.
In the GATE PCB-less LCD, a source drive circuit board is used to output the turn-off (“OFF”) voltage (referred to as Voff) and the turn-on voltage (referred to as Von), which are used to drive the gate lines, to the gate drive circuits, and to output the common voltage (referred to as Vcom) used by the common electrode lines. Because of the resistance of the wirings on the array substrate that connect the source drive circuit board with the gate drive circuits, there exists a variation of Voff among the gate drive circuits (one gate drive circuit is used to transmit signal to one gate line) and a variation of Vcom among the common electrode lines. In addition, for each pixel unit, in the case that parasitic capacitance is formed between the data line and the common electrode line on the array substrate and parasitic capacitance is formed between the gate line and the data line, a ripple of Vcom and a ripple of Voff occur due to the influence of the data signal, and the magnitude and the waveform of the ripples of Vcom and Voff are similar. The variation and ripple of Vcom and Voff are especially significant between the first gate drive circuit and the second gate drive circuit, because the amount of the current flowing through the first gate drive circuit and the second gate drive circuit is the largest and thereby the voltage drop is also the largest. In contrast, Von, of the gate lines are almost not subject to the aforementioned variation and ripple, due to its short duration, and thus Von at one gate drive circuit is almost the same as that at another gate drive circuit, i.e., Von is relatively uniform among the gate drive circuits.
FIG. 1 is a waveform diagram showing Voff in a conventional GATE PCB-less LCD.
The solid lines a and a′ in FIG. 1 are Voff of the first gate drive circuit, and the dashed lines b and b′ are Voff of the second gate drive circuit. The lines a and b represent the waveforms of Voff under positive data signal (Positive DATA), and the lines a′ and b′ represent the waveforms of Voff under negative data signal (Negative DATA). As shown in FIG. 1, in the GATE PCB-less LCD, the variation and ripple of Voff become more significant with the gate drive circuit of a bigger serial number.
Since Von is relatively uniform among the gate drive circuits and Voff is subject to the above variation and ripple, the difference of the Von and Voff at one gate drive circuit differs from that at another gate drive circuit. The difference of Von and Voff is referred to as ΔVg, which is an important factor influencing the charging characteristic of a pixel electrode.
FIG. 2 is a diagram showing the variation of ΔVg between the first gate drive circuit and the second gate drive circuit. In FIG. 2, line a represents the waveform of the Voff at the first gate drive circuit, line b represents the waveform of Voff at the second gate drive circuit, and line d represents the waveform of Von at the first and second gate drive circuits; ΔVg-1 represents ΔVg at the first gate drive circuit; and ΔVg-2 represents ΔVg at the second gate drive circuit. As sown in FIG. 2, ΔVg-1 is larger than ΔVg-2, that is, ΔVg-1 and ΔVg-2 differ from each other. Because of the variation of ΔVg, the ripple of the charging amount (referred to as ΔVp) of a pixel electrode varies among different gate line circuits. ΔVp is caused by the parasitic capacitance formed by the pixel electrode and the gate line. When the gate line switches between Voff and Von, the ripple of the charging amount is generated due to the parasitic capacitance.
The relationship between ΔVp and ΔVg is expressed as follows:ΔVp=Cgd*ΔVg/Ctot  (1)Ctot=Cgd+C1c+Cs  (2),where Cgd is the parasitic capacitance between the gate line and the drain electrode, C1c stands for the liquid crystal capacitance, and Cs is the storage capacitance in parallel with the liquid crystal capacitance. Since Cgd, C1c, and C, are constants, ΔVp is proportional to ΔVg.
The variation of ΔVp among the pixel electrodes corresponding to the gate drive circuits causes an abnormal block image in the lateral direction (also referred to as Y-Block phenomenon). The so-called Y-Block phenomenon is referred to the phenomenon that a variation of the gray level occurs among the driving regions of the gate drive circuits. The Y-Block phenomenon occurs when there exists a variation of ΔVg among the gate drive circuits but does not occur when there is no variation of ΔVg. The Y-block phenomenon is an important factor that reduces the display quality of the liquid crystal display. The Y-Block phenomenon occurs when the variation of ΔVg exists, irrespective of the polarities of the data signals.